Protrusion of electroplated copper filled in through silicon vias during annealing process

• Autores: Si Chen, Fei Qin, Tong An, Pei Chen, Bing Xie, Xunqing Shi
• Localización: Microelectronics reliability, ISSN 0026-2714, Nº. 63, 2016, págs. 183-193
• Idioma: inglés
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• Resumen

  • Abstract To investigate the protrusion behavior of the copper filled in through silicon via (TSV), four sets of TSV copper samples are prepared by using four level sets of electroplating current density and additive concentration, and then the samples are annealed with three temperature ramp rates, 10 °C/min, 1.2 °C/min and 0.6 °C/min, respectively. Protrusion of the copper in all of the samples after annealing is measured, and the grain size of the copper before and after annealing is examined. A mechanism of grain size evolution is developed to explain the protrusion process during annealing. A finite element (FE) model is also built up and a grain size dependent material model is introduced to explain the effects of electroplating parameter and annealing temperature ramp rate. Experimental and numerical results show that the sample filled by higher electroplating current density and higher additive concentration has smaller copper grain size both before and after annealing, and also has less protrusion. The protrusion strongly depends on the grain size both before and after annealing. The annealing temperature ramp rate has significant impact on the grain size and protrusion after annealing. The temperature ramp rate affects the protrusion by influencing grain size evolution process, and the mechanism is also validated by FE analysis. After all, an optimized annealing temperature profile is proposed to minimize the copper protrusion by restraining the growth of grain during annealing.