IEICE transactions on electronics

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  Año 2005, Vol. 88, Número 4

  • Low-Power Design of High-Speed A/D Converters (INVITED)

    N. Kawai, D. Miyazaki, S. Kawahito, K. Honda, M. Furuta

    pág. 468

    

  • A 1-V Cyclic A/D Converter Using FD-SOI Sample/Hold Circuits for Sensor Networks

    Y. Kado, J. Terada, Y. Matsuya, S. Mutoh

    pág. 479

    

  • Sub-1-V Power-Supply System with Variable-Stage SC-Type DC-DC Converter Scheme for Ambient Energy Sources

    Y. Yoshida, F. Utsunomiya

    pág. 484

    

  • A 2.4-GHz Temperature-Compensated CMOS LC-VCO for Low Frequency Drift Low-Power Direct-Modulation GFSK Transmitters

    R. Terauchi, K. Hisano, H. Ishikuro, S. Kousai, H. Kobayashi, H. Majima, T. Tanzawa, K. Agawa, H. Shibayama

    pág. 490

    

  • CMOS Radio Design for Complete Single Chip GPS SoC

    N. Suzuki, T. Kadoyama, M. Katakura

    pág. 496

    

  • A 300-MHz-Band, Sub-1 V and Sub-1 mW CMOS SAW Oscillator Suitable for Use in RF Transmitters

    M. Kozaki

    pág. 502

    

  • Standby and Active Leakage Current Control and Minimization in CMOS VLSI Circuits (INVITED)

    F. Fallah, M. Pedram

    pág. 509

    

  • Dynamic Voltage and Frequency Management for a Low-Power Embedded Microprocessor

    M. Nakai, T. Meguro, Takahiko Kondo, A. Hashiguchi, H. Kawahara, K. Kumano, M. Shimura, T. Seki, S. Akui, K. Seno

    pág. 520

    

  • A 4500 MIPS/W, 86 muA Resume-Standby, 11 muA Ultra-Standby Application Processor for 3G Cellular Phones

    M. Yamaoka, Y. Shimazaki, M. Ozawa, S. Tamaki, M. Furuyama, M. Ishikawa, T. Kamei, Y. Kondo

    pág. 528

    

  • Low-Power Network-Packet-Processing Architecture Using Process-Learning Cache for High-End Backbone Router

    M. Okuno, S. I. Ishida

    pág. 536

    

  • An Energy-Efficient Clustered Superscalar Processor

    Takashi Sato, A. Chiyonobu

    pág. 544

    

  • A Resource-Shared VLIW Processor for Low-Power On-Chip Multiprocessing in the Nanometer Era

    K. Kobayashi, M. Aramoto, H. Onodera

    pág. 552

    

  • A Low-Power Systolic Array Architecture for Block-Matching Motion Estimation

    T. Matsuno, M. Miyama, J. Miyakoshi, Y. Murachi, K. Hamano

    pág. 559

    

  • An Exact Leading Non-Zero Detector for a Floating-Point Unit

    F. Arakawa, T. Hayashi, M. Nishibori

    pág. 570

    

  • Design Optimization of a High-Speed, Area-Efficient and Low-Power Montgomery Modular Multiplier for RSA Algorithm

    S. Masui, K. Mukaida, M. Takenaka

    pág. 576

    

  • A Sub-0.5 V Differential ED-CMOS/SOI Circuit with Over-1-GHz Operation

    T. Douseki, T. Shimamura

    pág. 582

    

  • Dynamic Power-Supply and Well Noise Measurements and Analysis for Low Power Body Biased Circuits

    S. Hirano, H. Tsujikawa, K. Shimazaki, M. Nagata, T. Okumoto

    pág. 589

    

  • Power Optimization of an 8051-Compliant IP Microcontroller

    L. Fanucci, S. Saponara

    pág. 597

    

  • A 13.56 MHz CMOS RF Identification Passive Tag LSI with Ferroelectric Random Access Memory (INVITED)

    S. Masui, T. Teramoto

    pág. 601

    

  • Improvement in Retention/Program Time Ratio of Direct Tunneling Memory (DTM) for Low Power SoC Applications

    T. Nakanishi, H. Tanaka, K. Tsunoda, A. Sato, H. Tashiro

    pág. 608

    

  • The Umbrella Cell: A High-Density 2T Cell for SOC Applications

    T. Ishikawa, S. Akiyama, T. Watanabe, N. Oodaira

    pág. 614

    

  • Embedded Low-Power Dynamic TCAM Architecture with Transparently Scheduled Refresh

    T. Koide, K. Dosaka, K. Arimoto, K. Fujishima, H. Noda, K. Inoue, H. J. Mattausch

    pág. 622

    

  • 0.3-1.5 V Embedded SRAM Core with Write-Replica Circuit Using Asymmetrical Memory Cell and Source-Level-Adjusted Direct-Sense-Amplifier

    A. Shibayama, H. Akamatsu, H. Yamauchi, T. Suzuki, Y. Yamagami, I. Hatanaka

    pág. 630

    

  • FOREWORD

    E. Tokumitsu

    pág. 639

    

  • Electrical Characterization of Aluminum-Oxynitride Stacked Gate Dielectrics Prepared by a Layer-by-Layer Process of Chemical Vapor Deposition and Rapid Thermal Nitridation

    A. Suyama, H. Murakami, W. Mizubayashi, H. Yokoi

    pág. 640

    

  • Characterization of Atom Diffusion in Polycrystalline Si/SiGe/Si Stacked Gate

    D. Azuma, S. Higashi, H. Murakami, Y. Moriwaki, M. Fujitake

    pág. 646

    

  • Thermally Robust Nickel Silicide Process for Nano-Scale CMOS Technology

    Y. J. Kim, H. H. Ji, S. B. Huh, H. S. Cha, U. S. Kim, J. S. Wang, S. Y. Oh, J. G. Yun, B. F. Huang

    pág. 651

    

  • Separation by Bonding Si Islands (SBSI) for Advanced CMOS LSI Applications

    H. Ohri, J. Murota, M. Sakuraba, T. Yamazaki, S. I. Ohmi, S. Morita

    pág. 656

    

  • Effects of Electric Field on Metal-Induced Lateral Crystallization under Limited Ni-Supply Condition

    G. Nakagawa, N. Shibata

    pág. 662

    

  • Low Temperature Poly-Si Thin Film Transistor on Plastic Substrates

    K. B. Park, J. S. Jung, J. M. Kim, Y. S. Park, J. Y. Kwon, D. Y. Kim, H. S. Y. Cho

    pág. 667