Microelectronics reliability

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  Año 2008, Vol. 48, Número 1

  • A study of nanoparticles in Sn¿Ag based lead free solders.

    M. Amagai

    págs. 1-16

    

  • A threshold voltage model for short-channel MOSFETs taking into account the varying depth of channel depletion layers around the source and drain.

    S. Baishya, A. Mallik, C.K. Sarkar

    págs. 17-22

    

  • A 2D threshold-voltage model for small MOSFET with quantum-mechanical effects.

    J.P. Xu, Y.P. Li, P.T. Lai, W.B. Chen, S.G. Xu, J.G. Guan

    págs. 23-28

    

  • Modeling the sensitivity of CMOS circuits to radiation induced single event transients.

    G.I. Wirth, M.G. Vieira, E.H. Neto, Fernanda G. L. Kastensmidt

    págs. 29-36

    

  • Methodology of semiconductor devices classification into groups of differentiated quality.

    A Konczakowska

    págs. 37-44

    

  • Electro-thermal modeling of multifinger AlGaN/GaN HEMT device operation including thermal substrate effects.

    E.R. Heller, Apolinar Crespo

    págs. 45-50

    

  • A new electrothermal average model of the diode¿transistor switch.

    K. Górecki

    págs. 51-58

    

  • Simultaneous mechanical and electrical straining of conventional thick-film resistors.

    Z. Stanimirovic, M.M. Jevtic, I. Stanimirovic

    págs. 59-67

    

  • A strategy for damage assessment of thermally stressed copper vias in microelectronic printed circuit boards.

    K. Weinberg, W.H. Müller

    págs. 68-82

    

  • Growth of tin whiskers for lead-free plated leadframe packages in high humid environments and during thermal cycling.

    Y. Nakadaira, S. Jeong, J. Shim, J. Seo, S. Min, T. Cho, S. Kang, S. Oh

    págs. 83-104

    

  • Whisker growth on tin finishes of different electrolytes.

    B. Jiang, A.-P. Xian

    págs. 105-110

    

  • Investigation of relation between intermetallic and tin whisker growths under ambient condition.

    K.S. Kim, C. H. Yu, S.W. Han, K.C. Yang, J. H. Kim

    págs. 111-118

    

  • Packaging parameter analysis and optimization design on solder joint reliability for twin die stacked packages by variance in strain energy density (SED) of each solder joint.

    C-Y. Mao, R.-S. Chen

    págs. 119-131

    

  • Reliability evaluations for board-level chip-scale packages under coupled power and thermal cycling test conditions.

    T.H. Wang, Y.-S. Lai, Y.-C. Lin

    págs. 132-139

    

  • Experimental and statistical study in adhesion features of bonded interfaces of IC packages.

    C.-H. Chien, T. Chen, W.-B. Lin, C.-C. Hsieh, Y.-D. Wu, C.-H. Yeh

    págs. 140-148

    

  • Numerical analysis of ultrasonic wire bonding: Part 2. Effects of bonding parameters on temperature rise.

    Y. Ding, J.-K. Kim

    págs. 149-157

    

  • Clock aligner based on delay locked loop with double edge synchronization.

    M. Stojcev, G. Jovanovic

    págs. 158-166