IEICE transactions on information and systems

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  Año 2002, Vol. 85, Número 10

  • Test Generation for Test Compression Based on Statistical Coding

    Hideyuki Ichihara

    págs. 1466-1473

    

  • Two Test Generation Methods Using a Compacted Test Table and a Compacted Test Plan Table for RTL Data Path Circuits

    T. Hosokawa

    págs. 1474-1482

    

  • Average Power Reduction in Scan Testing by Test Vector Modification

    Seiji Kajihara

    págs. 1483-1489

    

  • Hybrid BIST Design for n-Detection Test Using Partially Rotation Scan

    Y. Ichino

    págs. 1490-1497

    

  • Accomplishment for At-Speed BISR for Embedded DRAMs

    Y. Nagura

    págs. 1498-1505

    

  • High Quality Delay Test Generation Based on Multiple-Thershold Gate-Delay Fault Model

    M. Nakao

    págs. 1506-1514

    

  • Diagnosing Crosstalk Faults in Sequential Circuits Using Fault Simulation

    Haruhisa Takahashi

    págs. 1515-1525

    

  • Reduction of the Target Fault List and Fault Simulation Method for Crosstalk in Clock-Delayed Domino Circuits

    Kantero Shimizu

    págs. 1526-1533

    

  • IDDQ Test Time Reduction by High Speed Charging of Load Capacitors of CMOS Logic Gates

    M. Hashizume

    págs. 1534-1541

    

  • CMOS Open Defect Detection by Supply Current Measurement under Time-Variable Electric Field Supply

    M. Hashizume

    págs. 1542-1550

    

  • Analysis und Testing of Analog and Mixed-Signal Circuits by an Operation-Region Model

    Yukiya Miura

    págs. 1551-1557

    

  • EB-Testing-Pad Method and Its Evaluation by Actual Devices

    N. Kuji

    págs. 1558-1563

    

  • EB Tester Line Delay Fault Localization Algorithm for Combinational Circuits Considering CAD Layout

    K. Nomura

    págs. 1564-1570

    

  • A Debug System for Heterogeneous Multiple Processors in a Single Chip for Multimedia Communication

    N. Minegishi

    págs. 1571-1578

    

  • Symbolic Model Checking of Deadlock Free Property of Task Control Architecture

    H. Hiraishi

    págs. 1579-1586

    

  • Verifying Signal-Transition Consistency of High-Level Designs Based on Symbolic Simulation

    Kiyoharu Hamaguchi

    págs. 1587-1594

    

  • Framework of Timed Trace Theoretic Verification Revisited

    B. Zhou

    págs. 1595-1604

    

  • Sequential Redundancy Removal Using Test Generation and Multiple Strongly Unreachable States

    H. Yotsuyanagi

    págs. 1605-1608

    

  • Hybrid Schemes and Variable-Size Subblock TLBs: Aggressive Superpage Supports

    Chan Ho Park

    págs. 1609-1618

    

  • Arranging and Clustering Results of Information Filtering for Effective Concpetual Browsing

    Y. Qu

    págs. 1619-1627

    

  • Minimizing Up-Front Data Transmission on Web Based Vector GIS

    Yung Hwan Oh

    págs. 1628-1635

    

  • FLASH: Fast and Scalable Table-Lookup Engine Architecture for Telecommunications

    T. Hayashi

    págs. 1636-1644

    

  • Proof for the Equivalence between Some Best-First Algorithms and Depth-First Algorithms for AND/OR Trees

    A. Nagai

    págs. 1645-1653

    

  • Robust Face Detection Using a Modified Radial Basis Function Network

    L. Huang

    págs. 1654-1662

    

  • Wrinkly Surface Generated on Irregular Mesh by Using IST Generalized on Code Space and Multi-Dimensional Space: Unification of Interpolation Surface and Fractal

    Tadahiro Fujimoto

    págs. 1663-1677

    

  • Recognition of Shape-Changing Hand Gestures

    Mun Ho Jeong

    págs. 1678-1687

    

  • Disambiguating World Senses in Korean-Japanese Machine Translation by Using Semi-Automatically Constructed Ontology

    S. J. Kang

    págs. 1688-1697

    

  • Automatic Segmentation of a Brain Region in MR Images Using Automatic Thresholding and 3D Morphological Operations

    Tae Woo Kim

    págs. 1698-1709

    

  • Neural Filter with Selection of Input Features and Its Application to Image Quality Improvement of Medical Image Sequences

    Ken-ichi Suzuki

    págs. 1710-1718

    

  • A Novel Cryptosystem with Lock Generation and Sum-Difference Replacement Ladder

    V. R. L. Shen

    págs. 1719-1722