Microelectronics reliability

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  Año 2007, Vol. 47, Número 9-11

  • ESD protection strategies in advanced CMOS SOI ICs.

    M.G. Khazhinsky

    págs. 1313-1321

    

  • Oxide reliability below 3 nm for advanced CMOS: Issues, characterization, and solutions.

    D. Goguenheim, D. Pic, J.L. Ogier

    págs. 1322-1329

    

  • Reliability methods and standards.

    J. Bisschop

    págs. 1330-1335

    

  • An approach to statistical analysis of gate oxide breakdown mechanisms.

    C.M. Tan, N. Raghavan

    págs. 1336-1342

    

  • Virtual reliability assessment of integrated power switches based on multi-domain simulation approach.

    P. Solomalala, Joaquim Saiz Alcaine, M. Mermet-Guyennet, A. Castellazzi, M. Ciappa, X. Chauffleur, J.P. Fradin

    págs. 1343-1348

    

  • Lifetime estimation of analog circuits from the electrical characteristics of stressed MOSFETs.

    J. Martin-Martinez, S. Gerardin, R. Rodríguez, Montserrat Nafria i Maqueda, Xavier Aymerich Humet, A. Cester, A. Paccagnella, G. Ghidini

    págs. 1349-1352

    

  • Statistical analysis during the reliability simulation.

    C. Bestory, F. Marc, H. Levi

    págs. 1353-1357

    

  • Importance of multi-temp testing in automotive qualification and zero defects program.

    Z. Wang, P. Zeelen, H. Tigelaar

    págs. 1358-1361

    

  • Investigation of low temperature SRAM and ROM failures to enable the replacement of cold test insertion by room temperature test.

    S. Müller, P. Egger

    págs. 1362-1365

    

  • Applications of DCIV method to NBTI characterization.

    A. Neugroschel, G. Bersuker, R. Choi

    págs. 1366-1372

    

  • A comprehensive study of stress induced leakage current using a floating gate structure for direct applications in EEPROM memories.

    D. Pic, D. Goguenheim, J.L. Ogier

    págs. 1373-1377

    

  • Performance and reliability of SLS ELA polysilicon TFTs fabricated with novel crystallization techniques.

    D.C. Moschou, M.A. Exarchos, D.N. Kouvatsos, G.J. Papaioannou, A.T. Voutsas

    págs. 1378-1383

    

  • High voltage transistor degradation in NVM pump application.

    R. Bottini, S. Costantini, N. Galbiati, A. Ghetti, G. Ghidini, A. Mauri, C. Scozzari, A. Sebastiani

    págs. 1384-1388

    

  • Lifetime modeling of intrinsic gate oxide breakdown at high temperature.

    R. Moonen, P. Vanmeerbeek, G. Lekens, W. De Ceuninck, P. Moens, J. Boutsen

    págs. 1389-1393

    

  • Study of hot-carrier effects on power RF LDMOS device reliability.

    M. Gares, M.A. Belaïd, H. Maanane, M. Masmoudi, J. Marcon, K. Mourgues, PH. Eudeline

    págs. 1394-1399

    

  • Negative bias temperature instabilities in sequentially stressed and annealed p-channel power VDMOSFETs.

    D. Dankovic, I. Manic, V. Davidovic, S. Djoric-Veljkovic, S. Golubovic, N. Stojadinovic

    págs. 1400-1405

    

  • Gate charge behaviors in N-channel power VDMOSFETs during HEF and PBT stresses.

    M. Alwan, B. Beydoun, K. Ketata, M. Zoaeter

    págs. 1406-1410

    

  • Comparative study of NBTI as a function of Si film orientation and thickness in SOI pMOSFETs.

    S.J. Jang, D.H. Ka, C.G. Yu, K.-S. Kim, W.-J. Cho, J.T. Park

    págs. 1411-1415

    

  • Exceptional operative gate voltage induces negative bias temperature instability (NBTI) on n-type trench DMOS transistors.

    S. Aresu, W. Kanert, R. Pufall, M. Goroll

    págs. 1416-1418

    

  • Two-dimensional numerical simulations of 1/f noise by GR mechanisms in thin film transistors: Effects of induced defect technology.

    A. Boukhenoufa, L. Pichon, C. Cordier

    págs. 1419-1423

    

  • Influence of the manufacturing process on the electrical properties of thin (<4 nm) Hafnium based high-k stacks observed with CAFM.

    M. Lanza, M. Porti, Montserrat Nafria i Maqueda, G. Benstetter, W. Frammelsberger, H. Razinger, E. Lodermeier, G. Jaschke

    págs. 1424-1428

    

  • Accelerated testing for time dependent dielectric breakdown (TDDB) evaluation of embedded DRAM capacitors using tantalum pentoxide.

    A. Inani, V. Koldyaev, S. Graves

    págs. 1429-1433

    

  • Degradation of double-gate polycrystalline silicon TFTs due to hot carrier stress.

    F.V. Farmakis, G.P. Kontogiannopoulos, D.N. Kouvatsos, A.T. Voutsas

    págs. 1434-1438

    

  • Analysis of hot carrier effects in a 0.35 µm high voltage n-channel LDMOS transistor.

    H. Enichlmair, S. Carniello, J.M. Park, R. Minixhofer

    págs. 1439-1443

    

  • Holding voltage investigation of advanced SCR-based protection structures for CMOS technology.

    A. Tazzoli, F.A. Marino, M. Cordoni, A. Benvenuti, P. Colombo, E. Zanoni, G. Meneghesso

    págs. 1444-1449

    

  • Experimental and numerical analysis of current flow homogeneity in low voltage SOI multi-finger gg-NMOS and NPN ESD protection devices.

    M. Heer, S. Bychikhin, W. Mamanee, D. Pogany, A. Heid, P. Grombach, M. Klaussner, W. Soppa, B. Ramler

    págs. 1450-1455

    

  • Identification of the physical signatures of CDM induced latent defects into a DC¿DC converter using low frequency noise measurements.

    Y. Gao, N. Guitard, C. Salamero, Marise Bafleur, L. Bary, L. Escotte, P. Gueulle, L. Lescouzeres

    págs. 1456-1461

    

  • TLP Characterization of large gate width devices.

    P. Coppens, G. Jenicot, H. Casier, F. De Pestel, F. Depuydt, N. Martens, P. Moens

    págs. 1462-1467

    

  • Black¿s law revisited¿Nucleation and growth in electromigration failure.

    J.R. Lloyd

    págs. 1468-1472

    

  • Backend dielectric breakdown dependence on linewidth and pattern density.

    L. Milor, C. Hong

    págs. 1473-1477